The present invention relates to CCD structures, and particularly to CCD imagers.
The level of peripherals normally integrated with CCD imagers in the prior art has been quite primitive. This has presumably been due to the special processing requirements of the CCD imagers. Typically logic and driver circuitry has been constructed off chip, as has all but the most rudimentary of sense amplifiers. It is necessary to have some sort of sense amplifier on-chip, but the prior art has frequently used only a single source follower stage, or perhaps two source follower stages, to get a signal adequate to send to a more sophisticated amplifier off chip.
This processing-driven limitation has prevented development of "smart" CCD devices, and also in general retarded the general performance of CCD devices by restricting the signal-to-noise ratio improvements which could be attained by on-chip processing.
The present invention remedies this shortcoming in two ways.
First, the present invention provides a device structure, wherein JFET peripherals are provided with the same doping profile as is used to build (for example) a virtual phase CCD electrode.
Second, the present invention also provides a peripheral device configuration wherein both buried-channel and surface-channel MOSFETs, with a common drain supply voltage, are used.
Buried-channel MOSFETs give good low-noise performance, but only as long as their drain voltage is kept sufficiently low. A plot of noise spectral density at 200 kilohertz vs. drain voltage can be seen in FIG. 9a, on page 1718, of the article "Design and Performance of a Low-Noise Charge-Detection Amplifier for VPCCD Devices" by J. Hynecek, at page 1713 of the December, 1984 issue of the IEEE Transactions on Electron Devices, Vol. ED-31, which is hereby incorporated by reference.
When a buried-channel device is biased above saturation, hot electrons are believed to be generated in the channel, and will produce additional electron-hole pairs through impact ionization. In a buried-channel transistor, some of the generated holes will be confined in the potential well between the bulk channel and the silicon-silicon dioxide interface. The holes must then travel along the interface from the drain region to the vicinity of the source and finally to the substrate or along the side of the gate to the channel stops. If enough holes accumulate at the interface, the threshold voltage of the transistor will shift, and a drain current increase will be observed. This phenomenon becomes more acute as transistor gate width is increased, and it is also exacerbated by the potential barriers for holes which sometimes exist at the edge of the buried channel next to the thick field oxide region.
To avoid this noise problem of buried-channel devices, while retaining the good low-noise small-signal characteristics of such devices, the present invention teaches combination of surface-channel MOS transistors with buried-channel MOS transistors in CCD peripherals. The surface-channel transistor can be correctly biased for high output current levels by the levels provided from preceding low-noise buried-channel stages, using a common drain supply voltage (VDD) for both surface-channel and buried-channel devices. That is, the surface-channel MOS output stage permits the use of low-noise buried channel devices in the preceding stages, but avoids the necessity of biasing the buried-channel transistors into their high-noise regime for driving the output stage. The combination of the buried-channel and surface-channel transistors thus offers lower drain bias requirements, lower power consumption, lower output DC voltage, and, most importantly, superior noise performance.
A further advantage of the preferred embodiment of the present invention is that both the buried-channel and surface-channel MOSFET devices are provided in a CCD process using no more masks than would be required to fabricate an MOS peripheral in any case.
In the most preferred embodiment of the present invention, the peripherals include JFETs and buried-channel MOSFETS and surface-channel MOSFETS. For example, in a sense amplifier having multiple source follower stages (as is commonly used), a buried-channel MOSFET with a JFET load can be used as the first-stage source follower, and a surface-channel MOSFET with a JFET load can be used as the output stage source follower.
Integration of these peripheral structures with virtual phase CCD technology is particularly convenient, but the present invention is also applicable to other CCD technologies, although it may not be as advantageous in every case.
In virtual phase technology the virtual electrode (which is a diffused electrode) provides an implant profile which can also be patterned in the periphery to provide JFET gates. Moreover, the well implants provide appropriate implant profiles for LDD (lightly-doped-drain-extension) regions which are self-aligned to the poly gate of an MOS transistor. Moreover, the channel implant used in the preferred version of virtual phase CCD array fabrication can be patterned to define separate surface-channel and buried-channel devices.
A further class of embodiments of the present invention provides two types of JFETs: both high-pinchoff (V.sub.p &gt;3 V) and low-pinchoff (V.sub.p &lt;3 V) devices are provided without use of any additional masking steps besides those already required for fabrication of the CCD array. This is advantageous since it gives the designer more options, particularly in designing low-noise circuits. In particular, high-pinchoff JFETs have a lower noise figure than low-pinchoff devices, so it may be advantageous to use the high-pinchoff devices for small-signal amplifier stages. High-pinchoff devices will pass much more current for a given geometry than low-pinchoff devices will, so the most advantageous configuration is to use both high-pinchoff and also low-pinchoff JFETs. An even more advantageous configuration is to use both high-pinchoff and also low-pinchoff JFETs together with both buried-channel and surface channel MOSFETs.
The use of JFETs and buried-channel MOSFETS and surface-channel MOSFETs is thus particularly convenient with virtual phase technology. However, it would also be convenient with any other CCD technology which used both one or more insulated-gate-electrode phases and also one or more diffused-gate-phases.
The use of both buried-channel and surface-channel MOSFETs is particularly convenient with virtual phase technology, but would also be advantageous with any other CCD technology which used a patterned shallow implant (p-type or n-type) during fabrication of the CCD array.
According to the present invention there is provided: A CCD device comprising: a substrate having a p-type crystalline semiconductor upper portion containing a plurality of CCD elements connected in series, each said CCD element comprising an insulated-gate phase portion and a diffused-gate phase portion, each of said insulated gate phase portions and each of said diffused-gate phase portions including both a well region and a barrier region, said well regions of said diffused-gate phase portions comprising both an n-type channel region and a shallow highly-doped p-type semiconductor electrode overlying said channel region; and a plurality of amplifiers also formed in said crystalline semiconductor upper portion, said amplifiers including a plurality of JFETs, said JFETs severally comprising a gate electrode having approximately the same dopant concentration and junction depth as said shallow highly-doped p-type semiconductor electrode overlying said channel region.